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IS43R32400A
4Meg x 32 128-MBIT DDR SDRAM
FEATURES
ISSI
DEVICE OVERVIEW
(R)
PRELIMINARY INFORMATION FEBRUARY 2006
* * * * * * * * * * * * * * * * * * * *
Clock Frequency: 200, 166, 100 MHz Power supply (VDD and VDDQ): 2.5V SSTL 2 interface Four internal banks to hide row Pre-charge and Active operations Commands and addresses register on positive clock edges (CLK) Bi-directional Data Strobe signal for data capture Differential clock inputs (CLK and CLK) for two data accesses per clock cycle Data Mask feature for Writes supported DLL aligns data I/O and Data Strobe transitions with clock inputs Half-strength and Matched drive strength options Programmable burst length for Read and Write operations Programmable CAS Latency (3, 4, 5 clocks) Programmable burst sequence: sequential or interleaved Burst concatenation and truncation supported for maximum data throughput Auto Pre-charge option for each Read or Write burst 4096 refresh cycles every 32ms Auto Refresh and Self Refresh Modes Pre-charge Power Down and Active Power Down Modes Industrial Temperature Availability Lead-free Availability
ISSI's 128-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory array is internally organized as four banks of 32M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 32-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2. IS43R32400A 1M x32x4 Banks VDD: 2.5V VDDQ: 2.5V 144-ball BGA
KEY TIMING PARAMETERS
Parameter CLK Cycle Time (min.) CAS Latency = 5 CAS Latency = 4 CAS Latency = 3 CLK Frequency (max.) CAS Latency = 5 CAS Latency = 4 CAS Latency = 3 -5 5 5 5 200 200 200 -6 6 6 6 166 166 166 Unit ns ns ns MHz MHz MHz
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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Rev. 00D 02/15/06
1
IS43R32400A
FUNCTIONAL BLOCK DIAGRAM (X32)
CLK CLK CKE CS RAS CAS WE
COMMAND DECODER & CLOCK GENERATOR MODE REGISTER REFRESH CONTROLLER
ISSI
DM0-DM3
DATA IN BUFFER
32 32 4 4
(R)
I/O 0-31 DQS0-DQS3
SELF
A11
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
14
REFRESH CONTROLLER
DATA OUT BUFFER
32 32
VDD/VDDQ Vss/VssQ
REFRESH COUNTER
2 4096 4096 4096 4096
12
ROW DECODER
MULTIPLEXER
MEMORY CELL ARRAY
12
14
ROW ADDRESS LATCH
12
12
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
8
256 (x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN ADDRESS BUFFER
8
2
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IS43R32400A
PIN CONFIGURATION PACKAGE CODE: B 144-BALL FBGA (Top View) (12.00 mm x 12.00 mm Body, 0.8 mm Ball Pitch)
ISSI
(R)
1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M
DQS0 DM0 VSSQ DQ3 DQ4 VDDQ DQ6 NC DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ NC DM3 DQS3 VDDQ DQ27
VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ
DQ5 VSSQ VSSQ VSSQ VDD VSS VSSQ VSS VSS VSS VSS VSS VSS VDD A11 A3
VDD VSSQ VSSQ VSSQ DQ26 DQ25 VSS VSSQ VSS VSS VSS VSS VSS VSS VDD A9 A4 VDD VDDQ DQ24
DQ7 VDDQ VDD
DQ17 DQ16 VDDQ VSSQ VSS DQ19 DQ18 VDDQ VSSQ VSS DQS2 DM2 NC VSSQ VSS
VSS VSSQ VDDQ DQ15 DQ14 VSS VSSQ VDDQ DQ13 DQ12 VSS VSSQ NC DM1 DQS1
DQ21 DQ20 VDDQ VSSQ VSS DQ22 DQ23 VDDQ VSSQ VSS CAS RAS CS WE NC NC VDD NC BA0 VSS BA1 A0 A10 A2 A1
VSS VSSQ VDDQ DQ11 DQ10 VSS VSSQ VDDQ NC A5 A6 VSS NC A7 VDD CK A8 DQ9 NC CK DQ8 NC NC
CKE VREF
Note: Vss balls inside the dotted box are optional for purposes of thermal dissipation.
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3
IS43R32400A
PIN FUNCTIONS
Symbol A0-A11 Type Input Pin
ISSI
(R)
BA0, BA1
Input Pin
CAS CKE
Input Pin Input Pin
CLK, CLK
Input Pin
CS
Input Pin
DM0-DM3
Input Pin
DQS0-DQS3
Input/Output Pin
DQ0-DQ31
Input/Output Pin
NC RAS WE VDDQ VDD VREF VSSQ VSS 4
-- Input Pin Input Pin Power Power Power Power Power Supply Supply Supply Supply Supply Pin Pin Pin Pin Pin
Function (In Detail) Address inputs are sampled during several commands. During an Active command, A0-A11 select a row to open. During a Read or Write command, A0-A7 select a starting column for a burst. During a Pre-charge command, A8 determines whether all banks are to be pre-charged, or a single bank. During a Load Mode Register command, the address inputs select an operating mode. Bank Address inputs are used to select a bank during Active, Pre-charge, Read, or Write commands. During a Load Mode Register command, BA0 and BA1 are used to select between the Base or Extended Mode Register CAS is Column Access Strobe, which is an input to the device command along with RAS and WE. See "Command Truth Table" for details. Clock Enable: CKE High activates and CKE Low de-activates internal clock signals and input/output buffers. When CKE goes Low, it can allow Self Refresh, Pre-charge Power Down, and Active Power Down. CKE must be High during entire Read and Write accesses. Input buffers except CLK, CLK, and CKE are disabled during Power Down. CKE uses an SSTL 2 input, but will detect a LVCMOS Low level after VDD is applied. All address and command inputs are sampled on the rising edge of the clock input CLK and the falling edge of the differential clock input CLK. Output data is referenced from the crossings of CLK and CLK. The Chip Select input enables the Command Decoding block of the device. When CS is disabled, a NOP occurs. See "Command Truth Table" for details. Multiple DDR SDRAM devices can be managed with CS. These are the Data Mask inputs. During a Write operation, the Data Mask input allows masking of the data bus. DM is sampled on each edge of DQS. There are four Data Mask input pins for the x32 DDR SDRAM. Each input applies to DQ0-DQ7, DQ8-DQ15, DQ16-DQ23, or DQ24-DQ31. These are the Data Strobe inputs. The Data Strobe is used for data capture. During a Read operation, the DQS output signal from the device is edgealigned with valid data on the data bus. During a Write operation, the DQS input should be issued to the DDR SDRAM device when the input values on DQ inputs are stable. There are four Data Strobe pins for the x32 DDR SDRAM. Each of the four Data Strobe pins applies to DQ0-DQ7, DQ8DQ15, DQ16-DQ23, or DQ24-DQ31. The pins DQ0 to DQ31 represent the data bus. For Write operations, the data bus is sampled on Data Strobe. For Read operations, the data bus is sampled on the crossings of CK and CK. No Connect: This pin should be left floating. These pins could be used for 256Mbit or higher density DDR SDRAM. RAS is Row Access Strobe, which is an input to the device command along with CAS and WE. See "Command Truth Table" for details. WE is Write Enable, which is an input to the device command along with RAS and CAS. See "Command Truth Table" for details. VDDQ is the output buffer power supply. VDD is the device power supply. VREF is the reference voltage for SSTL 2. VSSQ is the output buffer ground. VSS is the device ground.
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IS43R32400A
COMMAND TRUTH TABLE
Function CKE (n - 1) CKE (n) Device Deselect (NOP) H x No Operation (NOP) H x (2) Burst Stop H H Read(3) H x (3) Write H x Bank and Row Activate H x Pre-charge select bank H x Pre-charge all banks H x Load Mode Register (Base) H x Load Extended Mode Register H x Auto Refresh H x Self Refresh L x CS H L L L L L L L L L L L RAS x H H H H L L L L L L L CAS x H H L L H H H L L L L WE x H L H L H L L L L H H BA1 x x x V V V V x L L x x
ISSI
BA0 x x x V V V V x L H x x
(R)
Address x x x V V V x x V V x x
Notes: 1. H = VIH, L = VIL, x = VIH or VIL, V = Valid Data. 2. This command only applies to Read command with Auto Pre-charge disabled. 3. Auto Pre-charge is enabled with A8 = H (x32).
DATA MASK TRUTH TABLE
Function Write Enable for Data Byte DQ0-DQ7 Write Disable for Data Byte DQ0-DQ7 Write Enable for Data Byte DQ8-DQ15 Write Disable for Data Byte DQ8-DQ15 Write Enable for Data Byte DQ16-DQ23 Write Disable for Data Byte DQ16-DQ23 Write Enable for Data Byte DQ24-DQ31 Write Disable for Data Byte DQ24-DQ31
Notes: 1. H = VIH, L = VIL, x = VIH or VIL, V = Valid Data.
CKE (n - 1) H H H H H H H H
CKE (n) x x x x x x x x
DM0 L H x x x x x x
DM1 x x L H x x x x
DM2 x x x x L H x x
DM3 x x x x x x L H
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IS43R32400A
DETAILED COMMAND TRUTH TABLE - SAME BANKS Function (n) NOP or Continue previous operation NOP or Continue previous operation Activate row Issue Auto Refresh Load the Base/ Extended Mode Register Start Read Burst Command (n) Deselect NOP Active Auto Refresh Load Mode Register Read Read Read Write Write(1) Write Pre-charge Pre-charge Pre-charge Burst Terminate Prior State (n - 1) Any Any Idle Idle Idle Row active Read underway Write underway Row active Read underway Write underway Row active Read underway Write underway Read underway CKE (n - 1) H H H H H H H H H H H H H H H CKE (n) CS H H H H H H H H H H H H H H H H L L L L L L L L L L L L L L
ISSI
RAS X H L L L H H H H H H L L L H H H L L L L L L L L H H H H H H H L H H H L L L L L L L
(R)
CAS WE X X
Start Write Burst
De-activate Row, start Pre-charge Truncate Read Burst, start Pre-charge Truncate Write Burst, start Pre-charge Terminate Read Burst
Note: 1. A Write command may be terminated only at the completion of the Read burst. However, a Burst Terminate can be transmitted to end the Read burst early so that a Write command can be asserted.
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IS43R32400A
DETAILED COMMAND TRUTH TABLE - DIFFERENT BANKS (bank b, then bank g)
Function (n) NOP or Continue previous operation NOP or Continue previous operation Issue any command to bank g otherwise valid Start Read Burst in bank g Command (n) Deselect NOP Any command Read Prior State (n - 1) Any Any Idle Row in bank b active, activating, or pre-charging Read underway in bank b (Auto Precharge disabled) Write underway in bank b (Auto Precharge disabled) Read underway in bank b (Auto Precharge enabled) Write underway in bank b (Auto Precharge enabled) Row in bank b active, activating, or pre-charging Read underway in bank b (Auto Precharge disabled) Write underway in bank b (Auto Precharge disabled) Read underway in bank b (Auto Precharge enabled) Write underway in bank b (Auto Precharge enabled) CKE (n - 1) H H H H CKE (n) CS H H H H H L X L
ISSI
RAS X H X H H X L H X H
(R)
CAS WE X X
Read
H
H
L
H
L
H
Read
H
H
L
H
L
H
Read
H
H
L
H
L
H
Read
H
H
L
H
L
H
Start Write Burst in bank g
Write
H
H
L
H
L
L
Write(1)
H
H
L
H
L
L
Write
H
H
L
H
L
L
Write(1)
H
H
L
H
L
L
Write
H
H
L
H
L
L
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IS43R32400A
ISSI
Command (n) Pre-charge Prior State (n - 1) CKE (n - 1) Row in bank b active, H activating, or pre-charging Read underway in H bank b (Auto Precharge disabled) Write underway in H bank b (Auto Precharge disabled) Read underway in H bank b (Auto Precharge enabled) Write underway in H bank b (Auto Precharge enabled) CKE (n) CS H L RAS L
(R)
DETAILED COMMAND TRUTH TABLE - DIFFERENT BANKS (bank b, then bank g) -cont.
Function (n) Start Pre-charge CAS WE H L
Pre-charge
H
L
L
H
L
Pre-charge
H
L
L
H
L
Pre-charge
H
L
L
H
L
Pre-charge
H
L
L
H
L
Note: 1. A Write command may be terminated only at the completion of the Read burst. However, a Burst Terminate can be transmitted to end the Read burst early so that a Write command can be asserted.
DETAILED COMMAND TRUTH TABLE - LOW POWER MODES
Function (n) Maintain Power Down Maintain Self Refresh Exit Power Down Exit Self Refresh Mode Enter Pre-Charge Power Down Mode Enter Active Power Down Mode Enter Self Refresh Mode Command (n) don't care don't care Deselect or NOP Deselect or NOP Deselect or NOP Deselect or NOP Auto Refresh Prior State (n - 1) CKE (n - 1) CKE (n) Power Down Mode L L Self Refresh Mode L L Power Down L H Self Refresh Mode L H All Banks Idle H L Bank(s) Active All Banks Idle H H L L CS X X X X X X L RAS CAS WE X X X X X X X X X X X X X X X X L X L X H
8
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IS43R32400A
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD MAX VDDQ MAX VIN, VREF VOUT PD MAX ICS TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage, Reference Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Com. Ind. Storage Temperature Rating -0.3 to +3.6 0.3 to +3.6 -0.3 to VDDQ + 0.3 -0.3 to VDDQ + 0.3 2 50 0 to +70 -40 to +85 -55 to +150 Unit V V V V W mA C C
ISSI
(R)
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to Vss.
RECOMMENDED DC OPERATING CONDITIONS (SSTL_2 Input/Output, TA = 0oC to +70oC)
Symbol VDD VDDQ VTT VIH VIL VREF IIL IOL VOH VOL Parameter Test Condition Min Supply Voltage 2.375 I/O Supply Voltage 2.375 I/O Termination Voltage VREF - 0.04 Input High Voltage VREF + 0.15 Input Low Voltage VSSQ - 0.3 I/O Reference Voltage 0.49 x VDDQ Input Leakage Current 0 VREF VDD, with all inputs -5 at VSS, except tested input Output Leakage Current Output disabled; -5 0V VOUT VDDQ Output High Voltage IOH = -15.2mA VTT + 0.76 Level Output Low Voltage IOL = +15.2mA -- Level Typ. 2.500 2.500 VREF -- -- 0.5 x VDDQ -- -- -- -- Max 2.625 2.625 VREF + 0.04 VDDQ + 0.3 VDDQ - 0.15 0.51 x VDDQ 5 5 -- VREF - 0.76 Unit V V V V V V A A V V
Note: 1. VDDQ must always be less than or equal to VDD.
CAPACITANCE CHARACTERISTICS (At TA = 0 to +25C, VDD = VDDQ = 2.5V, f = 1 MHz)
Symbol CIN1 CIN2 CIN3 COUT Parameter Input Capacitance: Address, B0, B1 Input Capacitance:All other input pins Data Mask Input/Output Capacitance: DM0-DM3 Data Input/Output Capacitance: DQ and DQS Min. 4 3 6 6 Max. 5 5 8 8 Unit pF pF pF pF
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IS43R32400A
DC ELECTRICAL CHARACTERISTICS (VDD = 2.5V +/- 5%, TA = 0oC to +70oC)
Symbol Parameter IDD0 Operating Current Test Condition One bank operation; Active-Precharge; DQ, DM and DQS inputs change once per clock cycle; Address and Control inputs change once per two clock cycles; tRC = tRC (min); tCK = tCK (min) One bank operation; Active-Read-Precharge; BL = 4; CL = 4; Address and Control inputs change once per clock cycle; tRCDRD = 4 x tCK; tRC = tRC (min); tCK = tCK (min); IOUT = 0mA; All banks Idle; tCK = tCK (min); CKE = Low All banks idle; Address and control inputs change once per clock cycle; CKE = High; CS = High (Deselect); VIN = VREF for DQ, DQS, and DM; tCK = tCK (min) One bank Active; CKE = Low; tCK = tCK (min) One bank Active; CS = High; CKE = High; Address and Control inputs change once per clock cycle; DQ, DQS, and DM change twice per clock cycle; tRC = tRC (max); tCK = tCK (min) One bank Active; BL = 2; Address and Control inputs change once per clock cycle; tCK = tCK (min); IOUT = 0mA One bank Active; BL = 2; Address and Control inputs change once per clock cycle; DQ, DQS, DM change twice per clock cycle; tCK = tCK (min) tRC = tRFC (min); tCK = tCK (min) CKE 0.2V; tCK = tCK (min) Four bank interleaved Reads with Auto Precharge; BL = 4; Address and Controls inputs change per Read, Write, or Active command; tRC = tRC (min); tCK = tCK (min)
ISSI
(R)
Unit
160
mA
IDD1
Operating Current
IDD2P IDD2N
Precharge Power-Down Standby Current Idle Standby Current
240 40
mA mA
IDD3P IDD3N
Active Power-Down Standby Current Active Standby Current
80 40
mA mA
100 420
mA mA
IDD4R IDD4W
Operating Current Burst Read Operating Current Burst Write Auto Refresh Current Self Refresh Current Operating Current
IDD5 IDD6 IDD7
270 280 3
mA mA mA
550
mA
Notes: 1.Operating outside the "Absolute Maximum Ratings" may lead to temporary or permanent device failure. 2.Power up sequence describe in "Initialization" section. 3. All voltages are referenced to VSS.
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IS43R32400A
ISSI
-5 -6 Max. 10 10 10 0.55 0.55 0.7 0.85 0.45 1.1 0.6 1.15 -- -- 0.6 0.6 0.6 -- -- -- -- -- -- -- 100K -- -- -- -- -- -- -- -- -- -- -- 7.8 Min. 6 6 6 0.45 0.45 -0.7 Max. 10 10 10 0.55 0.55 0.7 Test Condition CL = 3 CL = 4 CL = 5 Min. 5 5 5 0.45 0.45 -0.7 -0.85 -- 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.5 0.7 tCH or tCL tHP - 0.5 12 14 8 4 2 3 2 2 2 1 2 7 200 tIS + 2 x tCK --
(R)
AC ELECTRICAL CHARACTERISTICS (VDD = 2.5V +/- 5%, TA = 0oC to +70oC) Symbol tCK Parameter Clock Cycle Time Unit ns ns ns tCK tCK ns ns ns tCK tCK tCK ns ns tCK tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns s
tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tDS tDH tHP tQH tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR tCDLR tCCD tMRD tDAL tXSA tPDEX tREF
Clock High Level Width Clock Low Level Width DQS-Out Access Time from CLK, CLK Output Access Time from CLK, CLK DQS-DQ Skew Read Preamble Read Postamble CLK to Valid DQS-In DQS-In Setup Time DQS-In Hold Time DQS Write Post Postamble DQS-In High Level Pulse Width DQS-In Low Level Pulse Width Address and Control Input Setup Time DQ and DM Setup Time to DQS DQ and DM Hold Time to DQS Clock Half Period Output DQS Valid Window Row Cycle Time Refresh Row Cycle Time Row Active Time RAS to CAS Delay in Read RAS to CAS Delay in Write Row Pre-charge Time Row Active to Row Active Delay Write Recovery Time Last Data-In to Read Command Column Address to Column Address Delay Mode Register Load Delay Auto Pre-charge Write Recovery + Pre-charge Self Refresh Exit to Read Command Delay Power Down Exit Time Refresh Interval Time
-0.85 0.85 -- 0.45 0.9 1.1 0.4 0.6 0.85 1.15 0 -- 0.35 -- 0.4 0.6 0.4 0.6 0.4 0.6 0.9 -- 0.5 -- 0.7 -- tCH or tCL -- tHP - 0.55 -- 11 -- 12 -- 7 120K 4 -- 2 -- 3 -- 2 -- 2 -- 2 -- 1 -- 2 -- 7 -- 200 -- tIS + 2 x tCK -- -- 7.8
Notes: 1. Operating outside the "Absolute Maximum Ratings" may lead to temporary or permanent device failure. 2. Power up sequence describe in "Initialization" section. 3. All voltages are referenced to Vss.
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IS43R32400A
AC TEST CONDITIONS Output Load
ISSI
(R)
VTT = 0.5 x VDDQ
Z = 25 Output 30 pF
25
VREF = 0.5 x VDDQ
AC TEST CONDITIONS
Parameter Input Signal Levels Input Signal Slew Rate Input Timing Reference Level Output Timing Measurement Reference Level CLK and CLK Signal Maximum Peak Swing Reference Level of Input/Ouput Signals Unit VREF + 0.4V / VREF - 0.4V 1V / ns VREF VTT 1.5V 0.5 x VDDQ
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IS43R32400A
FUNCTIONAL DESCRIPTION
The 128Mbit DDR SDRAM is a high-speed CMOS device with four banks that operate at 2.5V. Each 32Mbit bank is organized as 4,096 rows of 256 columns for the x32 options. Pre-fetch architecture allows Read and Write accesses to be double-data rate and burst oriented. Accesses start at a selected column location and continue every half-clock cycle for a programmed number of times. The Read or Write operation begins with an Active command to transmit the selected bank and row (A0-A11 bits are sampled). This is followed by a Read or Write command to sample the address bits again to determine the first column to access. When access to the memory is not necessary, the device can be put into a Power Down mode in which current consumption is minimized. Prior to normal operation, the device must be initialized in a defined procedure to function properly. The following sections describe the steps of initialization, the mode register definitions, command descriptions, and device operation.
ISSI
INITIALIZATION
(R)
The DDR SDRAM must be powered-on and initialized in a series of defined steps for proper operation. First, power is applied simultaneously to VDD and VDDQ. After these reaching stable values, a VREF is ramped up. If this sequence is not followed, latchup could occur and cause damage to the device. The input CKE must be asserted and held to a LVCMOS Low level during this time to prevent unwanted commands from being executed. The outputs I/O and DQS remain in high impedance until driven during a normal operation. Once VDD, VDDQ, VREF, and CKE are stable values, the clock inputs can begin to be applied. For a time period of at least 200s, valid CLK and CLK cycles must be applied prior to any command being issued to the device. CKE needs to then be raised to SSTL 2 logic High and issue a NOP or Deselect command to initialize the internal logic of the DRAM. Next, a Pre-charge All command is given to the device, followed by a NOP/Deselect command on each clock cycle for at least tRP. The Load Extended Mode Register should be issued to enable DLL, followed by another series of NOP/Deselect commands for at least tMRD. After this time, the Load Mode Register command should be issued to reset the DLL, again followed by a series of NOP or Deselect commands for at least tMRD. (Note: whenever the DLL is reset, 200 clock cycles must occur prior to any Read command.) The Pre-charge command is then issued, with NOP/ Deselect commands for at least tRP. Next, two AutoRefresh commands are issued, each followed by NOP/Deselect commands for at least tRFC. At this point, the JEDEC specification recommends that a DDR SDRAM receive another Load Mode Register command to clear the DLL, with NOP/Deselect commands for at least tMRD. The device is now ready to receive a valid command for normal operation.
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IS43R32400A
MODE REGISTER DEFINITION
The mode register allows configuration of the operating mode of the DDR SDRAM. This register is loaded as a step in the normal initialization of the device. The Load Mode Register command samples the values on inputs A0-A11, BA0 (Low) and BA1 (Low) and stores them as register values M0-M13. The values in the register determine the burst length, burst type, CAS latency timing, and DLL Reset/Clear. It should be noted that some bit values are reserved and should not be loaded into the register. The data in the mode register is retained until it is re-loaded or the DDR SDRAM loses its power (except for bit M8, which is cleared automatically). The register can be
ISSI
loaded only if all banks are idle. After the Load Mode Register command, a minimum time of tMRD must pass before the subsequent command is issued.
(R)
CAS LATENCY
After a Read command is issued to the device, a latency of several clock cycles is necessary prior to the validity of data on the data bus. Also known as CAS Latency (CL), the value can be configured as 3, 4, or 5 depending on the bits M4-M6 loaded into the register. Some CL values are not defined for certain speed ratings, and if they are used, the device may not function properly.
MODE REGISTER DEFINITION
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus (Ax) Mode Register (Mx) Burst Length M2 0 0 0 0 1 1 1 1 Burst Type M3 0 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 Operating Mode M8 M7 0 0 10 ---- Operating Mode M13 M12 0 -- 0 -- M11 0 -- M10 0 -- M9 0 -- Mode Standard operation All Other States Reserved M6-M0 Defined Defined -- Mode Standard Operation Standard Operation w/DLL Reset All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved Reserved 3 4 5 Reserved Reserved Type Sequential Interleaved M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 M3=0 Reserved 2 4 8 Reserved Reserved Reserved Full Page M3=1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
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IS43R32400A
BURST LENGTH
The highest access throughput of this device can be achieved by using a burst of either Read or Write accesses. The number of accesses in each burst would be pre-configured to be 2, 4, 8, or full page as shown in Mode Register Definition (bits M0-M2). When a Read or Write command is given to the device, the address bits A0-A7 (x32) select the block of columns and the starting column for the subsequent burst. The accesses in this burst can only reference the selected block, and may wrap-around if a boundary is reached. The Burst Definition table indicates the relationship between the least significant address bits and the starting column. The most significant address bits can select any unique block of columns in the currently activated row. (Note: Full page bursts are possible only in Sequential Mode, with the starting address even.)
ISSI
BURST TYPE
(R)
Bursts can be made in either of two types: sequential or interleaved. The burst type is programmed during a Load Mode Register command (bit M3). During a Read or Write burst, the order of accesses is determined by burst length, starting column, and burst type, as indicated in the Burst Definition table.
DLL RESET/CLEAR
To cause a DLL reset, the bit M8 is set to 1 in the Load Mode Register command. When the DLL is reset, 200 clock cycles are required to occur prior to any Read operation. To clear the DLL for normal operation, the bit M8 is set to 0. This device does not require it, but JEDEC specifications require that any time that the DLL is reset, it later be cleared prior for normal operation.
BURST DEFINITION
Burst Length A2 2 0 4 0 1 1 0 0 0 8 0 1 1 1 1 Full Page (up to 256) Starting address n = A0-A7 0 0 1 1 0 0 1 1 Starting Column Address A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 ...Cn - 1, Cn... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported Sequential Order of Accesses in a Burst Interleaved
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IS43R32400A
EXTENDED MODE REGISTER DEFINITION
The Extended Mode Register is a second register to enable additional functions of the DDR SDRAM. This register is loaded as a step in the normal initialization of the device. The Load Extended Mode Register command samples the values on inputs A0-A11, BA0 (High) and BA1 (Low) and stores them as register values E0-E13. The additional functions are DLL enable/disable and output drive strength. Similarly to the Load Mode Register, the Load Extended Mode Register has reserved bit values, a bank idle prerequisite, and a tMRD time requirement. The data in the mode register is retained until it is reloaded or the device loses its power.
ISSI
DLL Enable/Disable
(R)
When the Load Extended Mode Register command is issued, DLL should be enabled (E0 = 0). Normal operation of the device requires this, but DLL can be disabled for debugging or evaluation, if necessary.
Output Drive Strength
Normal drive strength for the outputs is specified as SSTL 2. However, there are options for reduced drive strength included.
EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus (Ax) Mode Register (Ex)
Operating Mode
E13 0 -- E12 1 -- E11 0 -- E10 0 -- E9 0 -- E8 0 -- E7 0 -- Mode Standard Operation All Other States Reserved
DLL
E0 0 1 Status Enable Disable
Drive Strength
E6 0 0 1 -- E5 0 0 0 -- E4 0 0 0 -- E3 0 0 0 -- E2 0 0 0 -- E1 0 1 1 -- Type Full Strength Weak-60% Matched Impedence All Other States Reserved
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IS43R32400A
COMMANDS
All commands described in this section should be issued only when the initialization sequence is obeyed.
ISSI
Write
(R)
Deselect
This feature blocks unwanted commands from being executed. Chip select (CS) must be taken High to cause Deselect. Operations that are underway are not affected.
No Operation (NOP)
NOP is a command that prevents new commands from being executed. CS must be Low, while RAS, CAS, and WE must be High to issue NOP. NOP or Deselect commands must be issued during wait states to allow operations that are underway to continue uninterrupted.
The Write command is used to begin a burst write access. When the command is given to the device, the BA0 and BA1 inputs select the bank, and address bits A0-A7 (x32) select the block of columns and the starting column for the subsequent burst. The rising edge on the Data Strobe input(s) will cause the input values on the Data Mask pin(s) and I/O pins to be sampled for the write operation. The Auto Pre-charge function is one option in the Write command. If the Auto Pre-charge is enabled, the currently selected row will be Pre-charged following the Write burst. If the function is not enabled, the selected row will remain open for further accesses at the end of the Write burst.
Pre-charge
A Pre-charge command will de-activate an open row in a bank. The input A8 (x32) is sampled at this time to determine whether Pre-charge is applied to a single bank or all banks. After tRP, the bank has been precharged. It is de-activated, and goes into the idle state and must be activated before any Read or Write command can be issued to it. A Pre-charge command is treated as a NOP if either (a) the specified bank is already undergoing Pre-charge, or (b) the specified bank has no open row.
Load Mode Register
The Base Mode Register is loaded during a step of initialization to configure the DDR SDRAM. Load Mode Register (LMR) is issued when BA0 and BA1 are Low, and A0-A11 are selected according to the Mode Register Definition.
Load Extended Mode Register
The Extended Mode Register is loaded during a step of initialization to enable the DLL of the device. Load Extended Mode Register (LMR) is issued when BA0 is High, BA1 is Low, and A0-A11 are selected according to the Extended Mode Register Definition.
Auto Pre-charge
Auto Pre-charge is a feature that can be enabled as an option in a Read or Write command. If the input value on A8 (x32) is High during a Read or Write command, an automatic Pre-charge will occur just after the memory burst is completed. If the input value on A8 (x32) is Low, no Pre-charge will occur. With Auto Pre-charge, a minimum time of tRP must pass before the next command is issued to the same bank.
Read
The Read command is used to begin a burst read access. When the command is given to the device, the BA0 and BA1 inputs select the bank, and address bits A0-A7 (x32) select the block of columns and the starting column for the subsequent burst. The crossing of the CLK and CLK signals will cause the output values on the I/O pins to be valid. The Auto Precharge function is one option in the Read command. If the Auto Pre-charge is enabled, the currently selected row will be pre-charged following the Read burst. If the function is not enabled, the selected row will remain open for further accesses at the end of the Read burst.
Active
The Active command opens a row in preparation for a Read or Write burst. The row stays open for accesses until the bank receives a Pre-charge command. Other rows in the bank cannot be opened until the bank is de-activated with a Pre-charge command and another Active command is issued.
Burst Terminate
The Burst Terminate command truncates the burst of the most recently issued Read command (with Auto Pre-charge disabled). The open row being accessed in the Read burst remains open.
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IS43R32400A
Auto Refresh
The DDR SDRAM is issued the Auto Refresh command during normal operation to maintain data in the memory array. All the banks must be idle for the command to be executed. The device has 4096 refresh cycles every 32ms.
ISSI
open row will be pre-charged after completion of the Read burst. Unless stated otherwise, all timing diagrams for Read operations have disabled Auto Precharge.
(R)
Self Refresh
To issue the Self Refresh command, CKE must be Low. When the DDR SDRAM is in Self Refresh mode, it retains the data contents without external clocking, and ignores other input signals. The DLL is disabled upon entering the Self Refresh mode, and is enabled again upon leaving the mode. To exit Self Refresh, all inputs must be stable prior to CKE going High. Next, a NOP command command must be issued on each clock cycle for at least tXSNR to ensure that internal refresh operations are completed. To prepare for a memory access, the DDR SDRAM must receive a DLL reset followed by a NOP command for 200 clock cycles.
DEVICE OPERATION
Bank and Row Activation
An Active command must be issued to the DDR SDRAM to open a bank and row prior to an access. The row will be available for a Read or Write command once a time tRCD has occurred. The Active command is depicted in the figure. As CLK goes High, CS and RAS are Low, while CKE, WE, and CAS are High. Upon issuing the Active command, the values on the address inputs specify the row, and BA0 and BA1 specify the bank. When an Active command is issued for a bank and row, another row in that same bank may be activated after a time tRC. When an Active command is issued for a bank and row, a row in a different bank may be activated after a time tRRD. (Note: to ensure that time requirement tRCD, tRC, or tRRD is met, NOP commands should be issued for a whole number of clock cycles that is greater than the time requirement (ie. tRCD) divided by the clock period.)
The Read command causes data to be retrieved and placed in the pipeline. The subsequent command can be NOP, Read, or Terminate Burst. The data from the starting column specified in the Read command appears on I/O pins following a CAS latency of after the Read command. On each CLK and CLK crossing, the data from the next column in the burst sequence is output from the pipeline until the burst is completed (see Read Burst, Non-consecutive Read Burst, and Consecutive Read Burst). There are two cases in which a full Read burst length is not completed. The first is when the data retrieved from a subsequent Read burst interrupts the previous burst (see Random Read Accesses). The second is when a subsequent Burst Terminate command truncates the burst (see Terminating a Read Burst and Read to Write). The Burst Terminate and Read commands obey the same CAS latency timing such that they should be issued x cycles after a previous Read command, where x is the number of pairs of columns to output. By following a desired command sequence, continuous data can be output with either whole Read bursts or truncated Read bursts. Whenever a Read burst finishes and no other commands have been initiated, the I/O returns to High-Z. If Auto Pre-charge is not enabled in the Read burst, the Pre-charge command can be issued separately following the Read command. The Pre-charge command should be received by the device x cycles after the Read command, where x is the desired number of pairs of columns to output during the Read burst. After the Pre-charge command, it is necessary to wait until both tRAS and tRP have been met before issuing a new command to the same bank. Data Strobe output is driven synchronously with the output data on the I/O pins. The Low portion of the Data Strobe just prior to the first output data is the Read Pre-amble; and the Low portion coinciding with the last output data is the Read Post-amble. Before any Write command can be executed, any previous Read burst must have been completed normally or truncated by a Burst Terminate command. In the diagram Read to Write, a Burst Terminate command is issued to truncate a Read Burst early, and begin a Write operation. After the Write command, a time tDQSS is required prior to latching the data on the I/O.
Read Operation
A Read command starts a burst from an activated row. The Read command is depicted in the figure. As CLK goes High, CS and CAS are Low, while RAS, CKE, and WE are High. The values on the inputs BA0 and BA1 specify the bank to access, and the address inputs specify the starting column in the open row. If Auto Pre-charge is enabled in the Read command, the
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IS43R32400A
Write Operation
A Write command starts a burst from an activated row. The Write command is depicted in the figure. As CLK goes High, CS, WE, and CAS are Low, while CKE and RAS are High. The values on the inputs BA0 and BA1 specify the bank to access, and the address inputs specify the starting column in the open row. If Auto Pre-charge is enabled in the Write command, the open row will be pre-charged after completion of the Write burst and time tWR. Unless stated otherwise, all timing diagrams for Write operations have disabled Auto Pre-charge. The Write command in conjunction with Data Strobe inputs causes data to be latched and placed in the pipeline. The Low portion of the Data Strobe between the Write command and the first rising edge of the strobe is the Write Pre-amble; and the Low portion following the last input data is the Write Post-amble. A minimum time of tDQSS after the Write, the next command can be NOP or Write. The data that is to be written to the starting column specified in the Write command will be latched upon the first rising edge of Data Strobe input(s) DQS0-DQS3 (x32) after that Write command. On each Data Strobe transition from Low-to-High or High-to-Low, the input values on the I/ O are sampled, and enter pipeline to be written in the pre-determined burst sequence (see Write Burst, Consecutive Write to Write, and Non-consecutive Write to Write). A new Write command can be issued x cycles after a previous Write command, where x is the number of pairs of columns to input. By following a desired command sequence, continuous data can be input with either whole Write bursts or truncated Write bursts. Whenever a Write burst finishes and no other commands have been initiated, the I/O returns to High-Z. A Write burst may be followed by Read command, with or without truncating the Write burst. To avoid truncating the input data, the timing parameter tWTR should be obeyed before issuing the Read command (see Write to Read, Non-truncated). The period tWTR begins on the first positive clock edge after the last data input has been latched. The Write burst can be truncated deliberately by using the Data Mask feature and a Read command with an earlier timing (see Write to Read, Truncated). If Auto Pre-charge is not enabled in the Write burst, the Pre-charge command can be issued separately some time following the Write command. The procedure to execute it is similar to the procedure to transition from a Write burst to a Read burst. To avoid
ISSI
(R)
truncating the input data, the timing parameter tWR should be obeyed before issuing the Pre-charge command (see Write to Pre-charge, Non-truncated). The period tWR begins on the first positive clock edge after the last data input has been latched. The Write burst can be truncated deliberately by using the Data Mask feature and a Pre-charge command with an earlier timing (see Write to Pre-charge, Truncated). After the Pre-charge command, it is necessary to wait until tRP has been met before issuing a new command to the same bank.
Power Down Operation
When the DDR SDRAM enters Power Down mode, power consumption is greatly reduced. To enter the mode, several conditions must be met. There must be neither a Read operation, nor a Write operation underway in the device at CLK positive edge n - 1, with CKE stable High. Prior to CLK positive edge n, CKE should go Low. A Power Down mode is entered if the appropriate command is issued as CLK n goes High. (If the command at CLK n is Auto Refresh, the SDRAM enters Self Refresh mode.) If the command at CLK n is NOP or Deselect, the device will enter Precharge Power Down mode or Active Power Down mode. While in a Power Down mode, CKE must be stable Low, and CLK and CLK signals maintained, while other inputs are ignored. Pre-charge Power Down mode conserves additional power by freezing the DLL. To exit the Power Down mode, normal voltages and clock frequency are applied. Prior to CLK positive edge n, CKE should go High. A NOP or Deselect command at CLK n, allows a valid command to be issued at CLK positive edge n + 1. (If exiting Self Refresh mode, the DLL is automatically enabled, and the device must be prepared according to the section describing Self Refresh.)
Pre-charge Operation
When this command is issued, either a particular bank, or all four banks will be de-activated after a time period of tRP. The bank(s) will be available for a row access until that time has occurred. The Pre-charge command is depicted in the figure. As CLK goes High, CS, RAS, and WE are Low, while CKE and CAS are High. The values on the address inputs are Don't Care, except for the input A8 (x32), which determines whether a single bank is selected for Pre-charge, or all four banks. If A8 is Low, the inputs BA0 and BA1 select the single bank; however, if A8 is High, BA0 and BA1 are Don't Care. Once any bank has been pre-charged, it becomes idle. Before any row can have a Read or Write access, it must be activated.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00D 02/15/06
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IS43R32400A
ISSI
(R)
Timing Waveforms Figure 1. AC Parameters for Read Timing ( Burst Length =4)
Figure 2. AC Parameters for Write Timing (Burst Length=4 )
CK# CK CMD A0-11,
DQS
DM DQ
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IS43R32400A
ISSI
(R)
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00D 02/15/06
21
IS43R32400A
Figure 6. Write with Auto Precharge (Burst Length = 4)
ISSI
(R)
Figure 7. Read Burst Interrupt by Read (CAS Letancy =5, Burst Length = 4 )
Figure 8. Write Interrupted by Write (Burst Length =4)
Figure 9. Auto Refresh Timing
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Rev. 00D 02/15/06
IS43R32400A
ISSI
(R)
Figure 11. Precharge Command
tMRD
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Rev. 00D 02/15/06
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IS43R32400A
ISSI
Speed (ns) 5 5 6 6 Order Part No. IS43R32400A-5B IS43R32400A-5BL IS43R32400A-6B IS43R32400A-6BL Package 144-ball FBGA 144-ball FBGA, Lead-free 144-ball FBGA 144-ball FBGA, Lead-free
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Frequency 200 MHz 200 MHz 166 MHz 166 MHz
Industrial Range: -40C to +85C
Frequency 166 MHz 166 MHz Speed (ns) 6 6 Order Part No. IS43R32400A-6BI IS43R32400A-6BLI Package 144-ball FBGA 144-ball FBGA, Lead-free
24
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. 00D 02/15/06
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (144-Ball)
ISSI
o 0.45 +/- 0.05 (144X) A B C D E F G H J K L M E1 E e
(R)
1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M
12 11 10 9 8 7 6 5 4 3 2 1
e D1 D
A1 SEATING PLANE
A
Notes: 1. Controlling dimensions are in millimeters. 2. 0.8 mm Ball Pitch
mBGA - 12mm x 12mm
MILLIMETERS Sym. Min.
N0. Leads A A1 D D1 E E1 e 1.17 0.32 11.95 -- 11.95 -- --
INCHES Min. Typ. Max.
Typ. Max.
144 1.25 0.35 8.80 8.80 0.80 1.40 0.38 -- -- --
0.046 0.013 0.470 -- 0.470 -- --
0.049 0.055 0.014 0.015 0.472 0.346 0.472 0.346 0.031 0.474 -- 0.474 -- --
12.00 12.05 12.00 12.05
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 05/23/05

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